Analog video signal application is still popular everywhere, and using a line-lock analog PLL (Phase-lock loop) for tracking line period (H-Sync period) to recover data clock with low jitter is very important to capture the analog video.
Conventional method is to use HSync, either input from RGB video stream or from the voltage sliced CSync (Composite Sync, from YPbPr component video) to feed into the analog PLL, and use vertical blank period as the PLL COAST signal to maintain PLL speed.
However, the HSync or CSync do not maintain the same period during vertical blank. Even with the help from the COAST signal, the clock generated by the analog PLL still will decay slightly and/or accumulate.
The present invention has arisen to mitigate and/or obviate the afore-described disadvantages.